The present invention relates in general to integrated circuits, and in particular to a timing circuit for a dynamic sense amplifier for memory circuits.
When reading the content of a memory circuit, sense amplifiers are used to sense and amplify the signal stored in a memory cell. There are basically two types of sense amplifiers, dynamic and static. FIG. 1 shows a typical static sense amplifier and FIG. 2 is an example of a dynamic sense amplifier circuit. The cross-coupled inverters 202/204 and 206/208 of the dynamic sense amplifier operate as a latch with positive feedback. Because of the positive feedback, the dynamic sense amplifier is inherently much faster than a static sense amplifier. A dynamic sense amplifier also consumes much less power since it switches to zero power as soon as it has made a decision as compared to the static sense amplifier which continues to dissipate power indefinitely.
Furthermore, a dynamic sense amplifier is much better suited for certain types of circuits, such as synchronous memory circuits, where speed enhancing techniques such as post charge logic (described in U.S. Pat. No. 4,985,643) or skewed logic (described in U.S. Pat. No. 5,519,344) can be used. This is due to the fact that the output of a dynamic sense amplifier is a pulse whose propagation speed can be made faster using these techniques as compared to the level output of a static sense amplifier in a conventional circuit.
It is therefore desirable to use dynamic sense amplifiers for power and speed advantages. However, a major drawback of a strobed dynamic sense amplifier, an example of which is shown in FIG. 2, is that its operation is highly sensitive to the timing of the strobe signal. When a positive pulse arrives on the STRB input, the sense amplifier makes a decision based on the differential voltage on its inputs relative to any offset voltage the amplifier may have, and the decision is irreversibly latched. In the context of a memory circuit, for example, if strobed too early (i.e., before a large enough differential signal at its inputs has developed), the sense amplifier may latch wrong data. On the other hand, if strobed too late (i.e., after developing a larger signal), time is unnecessarily wasted, adding to valuable access time. The optimum timing for the strobe signal would require an aggressively early strobe, yet not so aggressive that the sense amplifier fails to operate properly.
In a memory circuit, there are a number of different factors that impact the timing of the strobe signal for a dynamic sense amplifier. The inputs of the sense amplifier connect to a complementary pair of bit lines whose capacitance directly affect the speed of operation. If, for example, on a particular die there is more capacitance on the bit lines than the average expected bit line capacitance, the signal will develop slower. The sense amplifier must therefore wait longer (i.e., delayed strobe). Conversely, for a die exhibiting lower bit line capacitance than average, the sense amplifier can be strobed earlier.
Variations in the size of a memory cell access transistor also directly impact the speed of operation for the dynamic sense amplifier. Because a memory cell access transistor is typically very narrow (e.g., a fraction of a micron), even the smallest variations in the size may significantly impact the speed of the circuit. In case of, for example, a particularly wide access transistor, there will be higher current which develops a signal on the bit lines faster. A narrower access transistor, on the other hand, develops a signal slower.
Another factor that directly affects the timing requirements of the dynamic sense amplifier is resistivity of a word line made of poly silicon. The poly silicon may be particularly high in resistance or particularly low in resistance from one die to another. If the poly silicon has high resistance, it takes a longer time for the signal on that word line to get to the memory cell to start developing a signal. If it exhibits lower resistance, the signal will develop more quickly.
To ensure proper operation of the sense amplifier under all process conditions, designers have been typically quite conservative in the amount of time by which the sense amplifier strobe signal is delayed after signal starts to develop. This of course results in slower access time for the memory circuit. An overly aggressive design, on the other hand, may result in faster memory circuits but would also significantly increase the number of malfunctioning parts.
There is therefore a need for techniques that optimize the timing performance of dynamic sense amplifiers in memory circuits.